A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template

Kissler D, Hannig F, Kupriyanov O, Teich J (2006)


Publication Type: Conference contribution

Publication year: 2006

Pages Range: 31-37

Conference Proceedings Title: Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC)

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APA:

Kissler, D., Hannig, F., Kupriyanov, O., & Teich, J. (2006). A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. In Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) (pp. 31-37).

MLA:

Kissler, Dmitrij, et al. "A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template." Proceedings of the 2nd International Workshop on Reconfigurable Communication-Centric System-on-Chips (ReCoSoC) 2006. 31-37.

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