Modeling and synthesis of communication subsystems for loop accelerator pipelines

Dutta H, Hannig F, Schmid M, Keinert J (2010)

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2010

Pages Range: 125-132

Article Number: 5540760

Conference Proceedings Title: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)

Event location: Rennes FR

ISBN: 9781424469673

DOI: 10.1109/ASAP.2010.5540760

Abstract

The communication synthesis for data transfer and synchronization between loop accelerators is a major challenge in streaming applications. The complexity of the problem arises from the fact that optimal memory mapping and address generation in communication subsystems for parallel data access and out-of-order communication depend on tiling and scheduling choices. This paper solves the problem of communication synthesis by leveraging the windowed synchronous data flow (WSDF) model for communication synthesis. In this context, an intermediate representation of communicating loops in the polyhedral model and a unified methodology for their projection onto the WSDF model is proposed. Finally, we present the architecture template, synthesis methodology, and overhead of the communication primitive. © 2010 IEEE.

Authors with CRIS profile

Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Moritz Schmid Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

How to cite

APA:

Dutta, H., Hannig, F., Schmid, M., & Keinert, J. (2010). Modeling and synthesis of communication subsystems for loop accelerator pipelines. In Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (pp. 125-132). Rennes, FR.

MLA:

Dutta, Hritam, et al. "Modeling and synthesis of communication subsystems for loop accelerator pipelines." Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010, Rennes 2010. 125-132.

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