A fault-tolerant, dynamically scheduled pipeline structure for chip multiprocessors

Beitrag bei einer Tagung


Details zur Publikation

Autor(en): Aliee H, Zarandi HR
Jahr der Veröffentlichung: 2011
Tagungsband: Proceedings of the 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP'11)
Seitenbereich: 324-337
ISBN: 9783642242694


Abstract


This paper presents a dynamically scheduled pipeline structure for chip multiprocessors (CMPs). This technique exploits existing Simultaneous Multithreading (SMT), superscalar chip multiprocessors' redundancy to provide low-overhead, and broad coverage of faults at the cost of performance degradation for processors. This pipeline structure operates in two modes: 1) high-performance and 2) highly-reliable. In high-performance mode, each core works as a real SMT, superscalar processor. Whereas, the main contribution of the highly-reliable mode is: 1) To enhance the reliability of the system without adding extra redundancy strictly for fault tolerance, 2) To detect both transient and permanent faults, and 3) To recover existing faults. The experimental results show that the diagnosis mechanism quickly and accurately diagnoses faults. The fault detection latency for this technique is equal to the pipeline length of the processor, while it provides high fault detection coverage. Moreover, the reliable processor can function quite capably in the presence of both transient and permanent faults, despite of not using redundancy beyond which is already available in a modern microprocessor. Also, in the highly-reliable mode, the static and dynamic power consumption is declined by 25% and 36%, respectively. © 2011 Springer-Verlag.



FAU-Autoren / FAU-Herausgeber

Aliee, Hananeh
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Autor(en) der externen Einrichtung(en)
Amirkabir University of Technology (AUT) / دانشگاه صنعتی امیرکبیر


Zitierweisen

APA:
Aliee, H., & Zarandi, H.R. (2011). A fault-tolerant, dynamically scheduled pipeline structure for chip multiprocessors. In Proceedings of the 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP'11) (pp. 324-337). Naples, IT.

MLA:
Aliee, Hananeh, and Hamid Reza Zarandi. "A fault-tolerant, dynamically scheduled pipeline structure for chip multiprocessors." Proceedings of the 30th International Conference on Computer Safety, Reliability and Security, SAFECOMP 2011, Naples 2011. 324-337.

BibTeX: 

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