Maestro: A High Performance AES Encryption/Decryption System

Beitrag bei einer Tagung
(Originalarbeit)


Details zur Publikation

Autorinnen und Autoren: Biglari M, Qasemi E, Pourmohseni B
Verlag: IEEE
Jahr der Veröffentlichung: 2013
Tagungsband: Proceedings of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS)
Seitenbereich: 145-148
ISBN: 9781479905621
Sprache: Englisch


Abstract

High
throughput AES encryption/decryption is a necessity for many of modern
embedded systems. This article presents a high performance yet cost
efficient AES system. Maestro can be used in a wide range of embedded
applications with various requirements and limitations. Maestro is about
one million times faster than the pure software implementation. The
Maestro architecture is composed of two major components; the soft
processor aimed at system initialization and control, and the hardware
AES engine for high performance AES encryption/decryption. A ten stage
implicit pipelined architecture is considered for the AES engine. Two
novel techniques are proposed in design of AES engine which enable it to
reach a throughput of 12.8 Gbps. First, tightly coupled encryption and
round key generation units in encryption unit, and second, ahead of time
round key generation in decryption unit. Altera DE2-115 development and
educational FPGA board is used as the platform for Maestro. In the
proposed architecture the DMA modules act as interfaces between data
sources and data sinks by loading the input data into AES engine and
taking encrypted and generated test data to target memories.


FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Biglari, Mehrdad
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Pourmohseni, Behnaz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

University of Tehran


Zitierweisen

APA:
Biglari, M., Qasemi, E., & Pourmohseni, B. (2013). Maestro: A High Performance AES Encryption/Decryption System. In Proceedings of the 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS) (pp. 145-148). Tehran, IR: IEEE.

MLA:
Biglari, Mehrdad, Ehsan Qasemi, and Behnaz Pourmohseni. "Maestro: A High Performance AES Encryption/Decryption System." Proceedings of the International Symposium on Computer Architecture and Digital Systems (CADS), Tehran IEEE, 2013. 145-148.

BibTeX: 

Zuletzt aktualisiert 2019-14-08 um 16:08