Techniques for on-demand structural redundancy for massively parallel processor arrays

Beitrag in einer Fachzeitschrift
(Originalarbeit)


Details zur Publikation

Autor(en): Teich J, Lari V, Tanase AP, Witterauf M, Khosravi F, Meyer B
Zeitschrift: Journal of Systems Architecture
Verlag: Elsevier
Jahr der Veröffentlichung: 2015
Band: 61
Heftnummer: 10
Seitenbereich: 615-627
ISSN: 1383-7621


Abstract


In this paper, we present techniques for providing on-demand structural redundancy for Coarse-Grained Reconfigurable Array (CGRAs) and a calculus for determining the gains of reliability when applying these replication techniques from the perspective of safety-critical parallel loop program applications. Here, for protecting massively parallel loop computations against errors like soft errors, well-known replication schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) must be applied to each single Processor Element (PE) rather than one based on application requirements for reliability and Soft Error Rates (SERs). Moreover, different voting options and signal replication schemes are investigated. It will be shown that hardware voting may be accomplished at negligible hardware cost, i. e. less than two percent area overhead per PE, for a class of reconfigurable processor arrays called Tightly Coupled Processor Arrays (TCPAs). As a major contribution of this paper, a formal analysis of the reliability achievable by each combination of replication and voting scheme for parallel loop executions on CGRAs in dependence of a given SER and application timing characteristics (schedule) is elaborated. Using this analysis, error detection latencies may be computed and proper decisions which replication scheme to choose at runtime to guarantee a maximal probability of failure on-demand can be derived. Finally, fault-simulation results are provided and compared with the formal analysis of reliability.



FAU-Autoren / FAU-Herausgeber

Khosravi, Faramarz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lari, Vahid
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Tanase, Alexandru-Petru Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Witterauf, Michael
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Autor(en) der externen Einrichtung(en)
McGill University


Zitierweisen

APA:
Teich, J., Lari, V., Tanase, A.-P., Witterauf, M., Khosravi, F., & Meyer, B. (2015). Techniques for on-demand structural redundancy for massively parallel processor arrays. Journal of Systems Architecture, 61(10), 615-627. https://dx.doi.org/10.1016/j.sysarc.2015.10.004

MLA:
Teich, Jürgen, et al. "Techniques for on-demand structural redundancy for massively parallel processor arrays." Journal of Systems Architecture 61.10 (2015): 615-627.

BibTeX: 

Zuletzt aktualisiert 2018-08-10 um 21:50