Hardware decompression techniques for FPGA-based embedded systems

Journal article
(Original article)


Publication Details

Author(s): Teich J, Beckhoff C, Koch D
Journal: ACM Transactions on Reconfigurable Technology and Systems
Publisher: Association for Computing Machinery (ACM)
Publication year: 2009
Volume: 2
Journal issue: 2
ISSN: 1936-7406
eISSN: 1936-7414


Abstract


In this work, we present hardware decompression accelerators for widening the bottleneck between slow nonvolatile memories on the one side and high-speed FPGA configuration interfaces and fast softcore CPUs on the other side. We discuss different compression algorithms suitable for a hardware accelerated decompression on FPGAs as well as on CPLDs. The algorithms will be investigated with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second under optimal conditions while only requiring slightly more than a hundred lookup tables. We will evaluate how these decompressors perform on configuration bitstreams for different FPGAs as well as for softcore CPU binaries © 2009 ACM.



FAU Authors / FAU Editors

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


How to cite

APA:
Teich, J., Beckhoff, C., & Koch, D. (2009). Hardware decompression techniques for FPGA-based embedded systems. ACM Transactions on Reconfigurable Technology and Systems, 2(2). https://dx.doi.org/10.1145/1534916.1534919

MLA:
Teich, Jürgen, Christian Beckhoff, and Dirk Koch. "Hardware decompression techniques for FPGA-based embedded systems." ACM Transactions on Reconfigurable Technology and Systems 2.2 (2009).

BibTeX: 

Last updated on 2018-27-10 at 14:50