Efficient hardware checkpointing: Concepts, overhead analysis, and implementation

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Koch D, Haubelt C, Teich J
Jahr der Veröffentlichung: 2007
Tagungsband: Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007)
Seitenbereich: 188-196
ISBN: 9781595936004


Abstract


Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an effective methodology to cope with faults. In this paper, we systematically extend the concept of checkpointing known from software systems to hardware tasks running on reconfigurable devices. We will classify different mechanisms for hardware checkpointing and present formulas for estimating the hardware overhead. Moreover, we will reveal a tool that takes over the burden of modifying hardware modules for checkpointing. Post-synthesis results of applying our methodology to different hardware accelerators will be presented and the results will be compared with the theoretical estimations. Copyright 2007 ACM.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Haubelt, Christian Prof. Dr.-Ing.
Technische Fakultät
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Koch, D., Haubelt, C., & Teich, J. (2007). Efficient hardware checkpointing: Concepts, overhead analysis, and implementation. In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007) (pp. 188-196). Monterey, CA, US.

MLA:
Koch, Dirk, Christian Haubelt, and Jürgen Teich. "Efficient hardware checkpointing: Concepts, overhead analysis, and implementation." Proceedings of the FPGA 2007: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA 2007. 188-196.

BibTeX: 

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