A highly parameterizable parallel processor array architecture

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Kissler D, Kupriyanov O, Hannig F, Teich J
Jahr der Veröffentlichung: 2006
Tagungsband: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006)
Seitenbereich: 105-112
ISBN: 9780780397286


Abstract


In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. The main advantages of the proposed architecture template are the possibility of partial and differential reconfiguration and the systematical classification of different architectural parameters which allow to trade-off flexibility and hardware cost. The applicability of our approach is tested in a case study with different interconnect topologies on an FFGA platform. The results show substantial flexibility gains with only marginal additional hardware cost. © 2006 IEEE.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Kissler, D., Kupriyanov, O., Hannig, F., & Teich, J. (2006). A highly parameterizable parallel processor array architecture. In Proceedings of the IEEE International Conference on Field Programmable Technology (FPT 2006) (pp. 105-112). Bangkok, TH.

MLA:
Kissler, Dmitrij, et al. "A highly parameterizable parallel processor array architecture." Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok 2006. 105-112.

BibTeX: 

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