Challenges and Potentials of Emerging Multicore Architectures

Stürmer M, Wellein G, Hager G, Köstler H, Rüde U (2009)


Publication Type: Conference contribution

Publication year: 2009

Publisher: Springer

Edited Volumes: High Performance Computing in Science and Engineering, Garching/Munich 2007 - Transactions of the 3rd Joint HLRB and KONWIHR Status and Result Workshop

City/Town: Berlin Heidelberg

Pages Range: 551-566

Conference Proceedings Title: High Performance Computing in Science and Engineering Garching-Munich 2007

Event location: Garching

ISBN: 978-3-540-69181-5

URI: http://www.springer.com/math/cse/book/978-3-540-69181-5

Abstract

We present performance results on two current multicore architectures, a STI (Sony, Toshiba, and IBM) Cell processor included in the new Playstation™ 3 and a Sun UltraSPARC T2 ("Niagara 2") machine. On the Niagara 2 we analyze typical performance patterns that emerge from the peculiar way the memory controllers are activated on this chip using the standard STREAM benchmark and a shared-memory parallel lattice Boltzmann code. On the Cell processor we measure the memory bandwidth and run performance tests for LBM simulations. Additionally, we show results for an application in image processing on the Cell processor, where it is required to solve nonlinear anisotropic PDEs.

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APA:

Stürmer, M., Wellein, G., Hager, G., Köstler, H., & Rüde, U. (2009). Challenges and Potentials of Emerging Multicore Architectures. In High Performance Computing in Science and Engineering Garching-Munich 2007 (pp. 551-566). Garching: Berlin Heidelberg: Springer.

MLA:

Stürmer, Markus, et al. "Challenges and Potentials of Emerging Multicore Architectures." Proceedings of the Third Joint HLRB and KONWIHR Status and Result Workshop, Garching Berlin Heidelberg: Springer, 2009. 551-566.

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