Efficient Architecture/Compiler Co-Exploration for ASIPs

Beitrag bei einer Tagung


Details zur Publikation

Autorinnen und Autoren: Fischer D, Teich J, Thies M, Weper R
Titel Sammelwerk: Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '02
Jahr der Veröffentlichung: 2002
Tagungsband: ACM SIG Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Seitenbereich: 27-34


Abstract


In this paper, we present an efficient exploration algorithm for architecture/compiler co-designs of application-specific instruction-set processors. The huge design space is spanned by processor architecture parameters as well as different compiler optimization strategies. The objective space is multi-dimensional including conflicting objectives such as hardware cost, execution time and code size. The goal of the presented exploration algorithm is to determine the set of Pareto-optimal designs and compiler settings for a given benchmark program. In a case study, while exploring Pareto-optimal designs for a given DSP benchmark program, we show that for a realistic architecture family, the huge search space may be reduced dramatically using proper techniques to prune search spaces that may not contain Pareto-optimal solutions. Finally, we analyse and present solutions on what is the best architecture for a mixture of benchmark programs, i.e., what are the best architecture/compiler co-designs to execute the DSPstone benchmark. Copyright 2002 ACM.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Universität Paderborn


Zitierweisen

APA:
Fischer, D., Teich, J., Thies, M., & Weper, R. (2002). Efficient Architecture/Compiler Co-Exploration for ASIPs. In ACM SIG Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 27-34). Grenoble, FR.

MLA:
Fischer, Dirk, et al. "Efficient Architecture/Compiler Co-Exploration for ASIPs." Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES2002),, Grenoble 2002. 27-34.

BibTeX: 

Zuletzt aktualisiert 2018-23-11 um 06:05