Partitioning Processor Arrays under Resource Constraints

Beitrag in einer Fachzeitschrift


Details zur Publikation

Autorinnen und Autoren: Teich J, Thiele L, Zhang L
Zeitschrift: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Verlag: Kluwer Academic Publishers
Jahr der Veröffentlichung: 1997
Band: 17
Heftnummer: 1
Seitenbereich: 5-20
ISSN: 1387-5485


Abstract


A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also local memories and constraints on the size of available memories. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Einrichtungen weiterer Autorinnen und Autoren

Eidgenössische Technische Hochschule Zürich (ETHZ) / Swiss Federal Institute of Technology in Zurich


Zitierweisen

APA:
Teich, J., Thiele, L., & Zhang, L. (1997). Partitioning Processor Arrays under Resource Constraints. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 17(1), 5-20.

MLA:
Teich, Jürgen, Lothar Thiele, and L Zhang. "Partitioning Processor Arrays under Resource Constraints." Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 17.1 (1997): 5-20.

BibTeX: 

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