Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays

Journal article


Publication Details

Author(s): Kissler D, Gran D, Salcic Z, Hannig F, Teich J
Journal: IEEE Embedded Systems Letters
Publisher: Institute of Electrical and Electronics Engineers
Publication year: 2011
Volume: 3
Journal issue: 2
Pages range: 58-61
ISSN: 1943-0663
eISSN: 1943-0671


Abstract


This letter presents a systematic approach to efficiently handle a very large number of power domains in modern coarse-grained reconfigurable arrays in order to tightly match the different computational demands of processed algorithms with corresponding power consumption. It is based on a new highly scalable and generic power control network and additionally uses the state-of-the-art common power format based front-to-backend design methodology for a fully automated implementation. The power management is transparent to the user and is seamlessly integrated into the overall reconfiguration process: reconfiguration-controlled power gating. Furthermore, for the first time, a coarse-grained reconfigurable case study design with as many as 24 switchable power domains with detailed results on power savings and overheads is presented. The application of the proposed technique results in 60% active leakage and 90% standby leakage power reduction for several digital signal processing algorithms. © 2009 IEEE.



FAU Authors / FAU Editors

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


External institutions with authors

University of Auckland


How to cite

APA:
Kissler, D., Gran, D., Salcic, Z., Hannig, F., & Teich, J. (2011). Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays. IEEE Embedded Systems Letters, 3(2), 58-61. https://dx.doi.org/10.1109/LES.2011.2124438

MLA:
Kissler, Dmitrij, et al. "Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays." IEEE Embedded Systems Letters 3.2 (2011): 58-61.

BibTeX: 

Last updated on 2019-25-06 at 08:47