Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge

Beitrag in einer Fachzeitschrift

Details zur Publikation

Autorinnen und Autoren: Reiche O, Häublein K, Reichenbach M, Schmid M, Hannig F, Teich J, Fey D
Zeitschrift: Journal of Systems Architecture
Verlag: Elsevier
Jahr der Veröffentlichung: 2015
Band: 61
Heftnummer: 10
Seitenbereich: 646-658
ISSN: 1383-7621


In the domain of image processing, often real-time constraints are required. In particular, in safety-critical applications, timing is of utmost importance. A common approach to maintain real-time capabilities is to offload computations to dedicated hardware accelerators, such as Field Programmable Gate Arrays (FPGAs). Designing such architectures is per se already a challenging task, but finding the right design point between achieving as much throughput as necessary while spending as few resources as possible is an even bigger challenge. To address this design challenge in the domain of image processing, several approaches have been presented that introduce an additional layer of abstraction between the developer and the actual target hardware. One approach is to use a Domain-Specific Language (DSL) to generate highly optimized code for synthesis by general purpose High-Level Synthesis (HLS) frameworks. Another approach is to instantiate a generic VHDL IP-Core library for local imaging operators. Elevating the description of image algorithms to such a higher abstraction level can significantly reduce the complexity for designing hardware accelerators targeting FPGAs. We provide a comparison of results for both approaches, a non-expert algorithm developer can achieve. Furthermore, we present an automatic optimization process to give the algorithm developer even more control over trading execution time for resource usage, that could be applied on top of both approaches. To evaluate our optimization procedure, we compare the resulting FPGA accelerators to highly optimized Graphics Processing Unit (GPU) implementations of several image filters relevant for close-to-sensor image and video processing with stringent real-time constraints, such as in the automotive domain.

FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Fey, Dietmar Prof. Dr.-Ing.
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Häublein, Konrad
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Reiche, Oliver
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Reichenbach, Marc Dr.-Ing.
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Schmid, Moritz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Reiche, O., Häublein, K., Reichenbach, M., Schmid, M., Hannig, F., Teich, J., & Fey, D. (2015). Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge. Journal of Systems Architecture, 61(10), 646-658.

Reiche, Oliver, et al. "Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge." Journal of Systems Architecture 61.10 (2015): 646-658.


Zuletzt aktualisiert 2018-10-08 um 04:55