Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays

Beitrag in einer Fachzeitschrift


Details zur Publikation

Autor(en): Dutta H, Hannig F, Ruckdeschel H, Teich J
Zeitschrift: Journal of Systems Architecture
Verlag: Elsevier
Jahr der Veröffentlichung: 2007
Band: 53
Heftnummer: 5
Seitenbereich: 300-309
ISSN: 1383-7621


Abstract


Processor array architectures are optimal platforms for computationally intensive applications. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor arrays apart from different levels of cache have a large number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. Innately the applications are data flow dominant and have almost no control flow, but the application of hierarchical partitioning techniques has the disadvantage of a more complex control flow. In a previous paper, the authors presented first time a methodology for the automated control path synthesis for the mapping of partitioned algorithms onto processor arrays. However, the control path contained complex multiplication and division operators. In this paper, we propose a significant extension to the methodology which reduces the hardware cost of the global controller and memory address generators by avoiding these costly operations. © 2006 Elsevier B.V. All rights reserved.



FAU-Autoren / FAU-Herausgeber

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Dutta, H., Hannig, F., Ruckdeschel, H., & Teich, J. (2007). Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays. Journal of Systems Architecture, 53(5), 300-309. https://dx.doi.org/10.1016/j.sysarc.2006.10.009

MLA:
Dutta, Hritam, et al. "Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays." Journal of Systems Architecture 53.5 (2007): 300-309.

BibTeX: 

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