Evaluation of a Processor Simulator Exemplified by a Radar Processing Algorithm

Rachuj S, Hartmann C, Fey D (2017)

Publication Type: Conference contribution, Conference Contribution

Publication year: 2017

Publisher: VDE Verlag

City/Town: Wien

Pages Range: 96-100

Conference Proceedings Title: Workshop Proceedings

Event location: Wien

ISBN: 978-3-8007-4395-7

Authors with CRIS profile

Sebastian Rachuj Lehrstuhl für Informatik 3 (Rechnerarchitektur) Christian Hartmann Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Rachuj, S., Hartmann, C., & Fey, D. (2017). Evaluation of a Processor Simulator Exemplified by a Radar Processing Algorithm. In Workshop Proceedings (pp. 96-100). Wien: Wien: VDE Verlag.

MLA:

Rachuj, Sebastian, Christian Hartmann, and Dietmar Fey. "Evaluation of a Processor Simulator Exemplified by a Radar Processing Algorithm." Proceedings of the ARCS 2017: 30th International Conference on Architecture of Computing Systems, Wien Wien: VDE Verlag, 2017. 96-100.

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