Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms

Beitrag in einer Fachzeitschrift

Details zur Publikation

Autorinnen und Autoren: Teich J, Bednara M
Zeitschrift: Journal of Supercomputing
Verlag: Springer Verlag (Germany)
Jahr der Veröffentlichung: 2003
Seitenbereich: 149-165
ISSN: 0920-8542


We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there exists no continuous design flow that allows automated generation of FPGA configuration data from a loop nest specified in a high level language. Here, we present a methodology for automatic generation of synthesizable VHDL code specifying a processor array and optimized for FPGA implementation.

FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Teich, J., & Bednara, M. (2003). Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. Journal of Supercomputing, 149-165.

Teich, Jürgen, and Marcus Bednara. "Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms." Journal of Supercomputing (2003): 149-165.


Zuletzt aktualisiert 2018-28-06 um 04:23