System-Level Synthesis Using Evolutionary Algorithms

Beitrag in einer Fachzeitschrift

Details zur Publikation

Autorinnen und Autoren: Blickle T, Teich J, Thiele L
Zeitschrift: Design Automation For Embedded Systems
Verlag: Springer Verlag (Germany)
Jahr der Veröffentlichung: 1998
Band: 3
Heftnummer: 1
Seitenbereich: 23-58
ISSN: 0929-5585


In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. The application and adaptation of an Evolutionary Algorithm to solve the tasks of optimization and design space exploration is described.

FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Einrichtungen weiterer Autorinnen und Autoren

Eidgenössische Technische Hochschule Zürich (ETHZ) / Swiss Federal Institute of Technology in Zurich


Blickle, T., Teich, J., & Thiele, L. (1998). System-Level Synthesis Using Evolutionary Algorithms. Design Automation For Embedded Systems, 3(1), 23-58.

Blickle, Tobias, Jürgen Teich, and Lothar Thiele. "System-Level Synthesis Using Evolutionary Algorithms." Design Automation For Embedded Systems 3.1 (1998): 23-58.


Zuletzt aktualisiert 2018-09-08 um 05:24