A Fine-Grained Configurable Cache Architecture for Soft Processors

Beitrag bei einer Tagung
(Originalarbeit)


Details zur Publikation

Autor(en): Biglari M, Barijough KM, Goudarzi M, Pourmohseni B
Verlag: IEEE
Jahr der Veröffentlichung: 2016
Tagungsband: 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS)
Seitenbereich: 1-6
ISBN: 978-1-4673-8023-2
Sprache: Englisch


Abstract

The
ever increasing density and performance of FPGAs, has increased the
importance and popularity of soft processors. The growing gap between
the speed of processors and memories can partly be compensated through
memory hierarchy. Since memory accesses follow a non-uniform
distribution, and vary from one application to another, variable
set-associative cache architectures have emerged. In this paper, a novel
cache architecture, primarily aimed at soft processors, is proposed to
address the variable access demands of applications, through dynamically
configurable line-associativity, with no memory overhead. The FPGA
implementation of the proposed architecture achieves an average miss
count reduction of 70% compared to the direct-mapped cache which
translates in 17% improvement in IPC, on 11 benchmarks.


FAU-Autoren / FAU-Herausgeber

Biglari, Mehrdad
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Pourmohseni, Behnaz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Biglari, M., Barijough, K.M., Goudarzi, M., & Pourmohseni, B. (2016). A Fine-Grained Configurable Cache Architecture for Soft Processors. In 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) (pp. 1-6). Tehran, IR: IEEE.

MLA:
Biglari, Mehrdad, et al. "A Fine-Grained Configurable Cache Architecture for Soft Processors." Proceedings of the 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2015), Tehran IEEE, 2016. 1-6.

BibTeX: 

Zuletzt aktualisiert 2018-30-07 um 15:08