Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autor(en): Gangadharan D, Sousa É, Lari V, Hannig F, Teich J
Verlag: IEEE Computer Society
Jahr der Veröffentlichung: 2015
Tagungsband: Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR)
Seitenbereich: 398-403
ISBN: 9781479982974


Abstract


The growing demand of computationally intensive algorithms/applications has resulted in the widespread acceptance of heterogeneous MPSoC platforms. The primary reason for this trend is due to the better performance and power efficiency exhibited by heterogeneous architectures consisting of standard processor cores and hardware accelerators. However, multiple processors accessing shared resources such as cache/memory and buses may lead to significant contention on them, thereby decreasing not only the performance, but also timing predictability. Moreover, the effect of shared resource contention worsens in the presence of multiple application scenarios with different execution and communication bandwidth requirements. To mitigate this problem, we first propose a Dynamic Bus Reconfiguration Policy (DBRP) that decides when to reconfigure a shared bus between Non-Preemptive Fixed Priority (NP-FP) and Time-Division Multiple Access (TDMA) scheduling. The required TDMA slot sizes are computed on-the-fly before NP-FP to TDMA reconfiguration such that deadlines of all Hard Real-Time (HRT) applications are satisfied and all Soft Real-Time (SRT) applications are serviced evenly. Our proposed DBRP has been implemented on a real MPSoC platform consisting of cores connected by the AMBA AHB. The case studies demonstrate that reconfiguration of bus arbitration ensures that communication deadline constraints of HRT applications are maximally satisfied with low hardware and reconfiguration overhead.



FAU-Autoren / FAU-Herausgeber

Gangadharan, Deepak
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lari, Vahid
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sousa, Éricles
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Gangadharan, D., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2015). Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) (pp. 398-403). Pacific Grove, CA, US: IEEE Computer Society.

MLA:
Gangadharan, Deepak, et al. "Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms." Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015, Pacific Grove, CA IEEE Computer Society, 2015. 398-403.

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