Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays

Beitrag bei einer Tagung


Details zur Publikation

Autor(en): Gangadharan D, Tanase AP, Hannig F, Teich J
Jahr der Veröffentlichung: 2014


FAU-Autoren / FAU-Herausgeber

Gangadharan, Deepak
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Tanase, Alexandru-Petru Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Gangadharan, D., Tanase, A.-P., Hannig, F., & Teich, J. (2014). Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays. Dresden, Germany.

MLA:
Gangadharan, Deepak, et al. "Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays." Proceedings of the DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES), Dresden, Germany 2014.

BibTeX: 

Zuletzt aktualisiert 2018-10-08 um 16:53