A combined space-time multiplex architecture for a stacked smart sensor chip
Loos A, Schmidt M, Fey D (2006)
Publication Type: Conference contribution
Publication year: 2006
Journal
Publisher: International Society for Optical Engineering; 1999
Edited Volumes: Proceedings of SPIE - The International Society for Optical Engineering
Conference Proceedings Title: Proc. SPIE, Vol. 6185 / Computer Architectures and Photonic Interconnects
Event location: Strasbourg, France
DOI: 10.1117/12.662287
Abstract
We present a fine-grain parallel processor architecture which considers particularly the requirements defined by future 3-dimensional (3D) stacked optoelectronic devices. The architecture concept is well-suited for novel detector arrays which are exploited in data communication applications based on high-speed VCSEL photonic interconnects as well as for optical sensing applications in smart CMOS camera chips. We assume the presence of a two-dimensional optoelectronic interface mounted on top of the stacked device. Such a vertical communication scheme is perfect for the realization of very compact and fast working devices in embedded systems, e.g. in gripper arms of robots.
Authors with CRIS profile
Michael Schmidt
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Dietmar Fey
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
How to cite
APA:
Loos, A., Schmidt, M., & Fey, D. (2006). A combined space-time multiplex architecture for a stacked smart sensor chip. In Proc. SPIE, Vol. 6185 / Computer Architectures and Photonic Interconnects. Strasbourg, France, FR: International Society for Optical Engineering; 1999.
MLA:
Loos, Andreas, Michael Schmidt, and Dietmar Fey. "A combined space-time multiplex architecture for a stacked smart sensor chip." Proceedings of the Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration, Strasbourg, France International Society for Optical Engineering; 1999, 2006.
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