A Low-Power 60-GHz Integrated Sixport Receiver Front-End in a 130-nm BiCMOS Technology

Völkel M, Dietz M, Weigel R, Hagelauer AM, Kissinger D (2017)


Publication Language: English

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Future Publication Type: Conference contribution

Publication year: 2017

Pages Range: 73-76

Event location: Nürnberg

DOI: 10.23919/EuMIC.2017.8230663

Abstract

Abstract—In this paper a 60 GHz monolithic low-power sixport
receiver front-end for high precision industrial radar systems is
presented. The measurement principle is based on the passive
superposition and power detection of two incident millimeterwave
signals. The integrated receiver has been designed using
a 0.13μm SiGe BiCMOS process from IHP (SG13G2) and
includes a low noise amplifier (LNA), the passive sixport structure
and four detectors. The signal processing in the baseband is
done with an ADC-board designed with components from Texas
Instruments and a Cyclone IV FPGA board. The integrated
receiver circuit has a size of 1320μm x 950μm and a low power
consumption of 73mW from a 3.3V supply.
 

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How to cite

APA:

Völkel, M., Dietz, M., Weigel, R., Hagelauer, A.M., & Kissinger, D. (2017). A Low-Power 60-GHz Integrated Sixport Receiver Front-End in a 130-nm BiCMOS Technology. In Proceedings of the European Microwave Integrated Circuits Conference (pp. 73-76). Nürnberg.

MLA:

Völkel, Matthias, et al. "A Low-Power 60-GHz Integrated Sixport Receiver Front-End in a 130-nm BiCMOS Technology." Proceedings of the European Microwave Integrated Circuits Conference, Nürnberg 2017. 73-76.

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