Limmer S, Fey D (2012)
Publication Type: Conference contribution
Publication year: 2012
Publisher: International Society for Optical Engineering; 1999
Edited Volumes: Proceedings of SPIE - The International Society for Optical Engineering
Conference Proceedings Title: Proc. SPIE 8267
Event location: San Francisco, California, USA
DOI: 10.1117/12.905888
A parallel board-level interconnection design is presented consisting of 32 channels, each operating at 10 Gbps. The hardware uses available optoelectronic components (VCSEL, TIA, pin-diodes) and a combination of planarintegrated free-space optics, fiber-bundles and available MEMS-components, like the DMD ™from Texas Instruments. As a specific feature, we present a new modular inter-board interconnect, realized by 3D fiber-matrix connectors. The performance of the interconnect is evaluated with regard to optical properties and power consumption. Finally, we discuss the application of the interconnect for strongly distributed system architectures, as, for example, in high performance embedded computing systems and data centers. © 2012 SPIE.
APA:
Limmer, S., & Fey, D. (2012). Design of a Highly Parallel Board-Level-Interconnection with 320 Gbps Capacity. In Proc. SPIE 8267. San Francisco, California, USA: International Society for Optical Engineering; 1999.
MLA:
Limmer, Steffen, and Dietmar Fey. "Design of a Highly Parallel Board-Level-Interconnection with 320 Gbps Capacity." Proceedings of the SPIE, San Francisco, California, USA International Society for Optical Engineering; 1999, 2012.
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