Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems

Abschlussarbeit
(Habilitationsschrift)


Details zur Publikation

Autor(en): Ziener D
Jahr der Veröffentlichung: 2017
Sprache: Englisch


Abstract


In this treatise,  my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined. The efficiency of reconfigurable systems can be improved by loading optimized data paths on-the-fly on an FPGA fabric.

This technique was applied to the acceleration of SQL queries  for large database applications as well as for image and signal processing applications. The focus was not only on performance improvements and resource efficiency, but also the energy efficiency has been significantly improved. In the area of reliability, countermeasures against radiation-induced faults and  aging effects for long mission times were investigated and applied to SRAM-FPGA-based satellite systems. Finally, to increase the security of cryptographic FPGA-based implementations against physical attacks, i.e., side-channel and fault injection analysis as well as reverse engineering, it is proposed to transform static circuit structures into dynamic ones by applying dynamic partial reconfiguration.



FAU-Autoren / FAU-Herausgeber

Ziener, Daniel Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Ziener, D. (2017). Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems (Habilitation).

MLA:
Ziener, Daniel. Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems. Habilitation, 2017.

BibTeX: 

Zuletzt aktualisiert 2018-10-08 um 22:26