Akerss Wavefront Planner - One of the fastest Stencil-based Path Planners on FPGAs
Schmidt M, Fey D (2012)
Publication Type: Conference contribution
Publication year: 2012
Edited Volumes: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012
Pages Range: 1-6
Conference Proceedings Title: Proceedings of the International Conference on ReConFigurable Computing and FPGAs
Event location: Cancun, Mexico
DOI: 10.1109/ReConFig.2012.6416727
Abstract
The efficient and fast processing of path planning algorithms based on stencil codes is a great challenge. On the one hand, these iterative approaches are advantageous because of their regular processing pattern and the characteristic to avoid problems of other path planning methods, like local minima in potential field algorithms. On the other hand, they are computational-and data-intensive because of their high number of required iterations. By comparing several algorithms based on stencil codes, we found one of the fastest and most efficient path planners for realization on FPGAs, Akers's wavefront planner. A processing of 33 maps per second with a resolution of 1024×1024 is possible on a midsize Virtex-5 FPGA achieved through a column-based processing scheme combined with an efficient internal data storage. © 2012 IEEE.
Authors with CRIS profile
Michael Schmidt
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Dietmar Fey
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
How to cite
APA:
Schmidt, M., & Fey, D. (2012). Akers’s Wavefront Planner - One of the fastest Stencil-based Path Planners on FPGAs. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (pp. 1-6). Cancun, Mexico, MX.
MLA:
Schmidt, Michael, and Dietmar Fey. "Akers’s Wavefront Planner - One of the fastest Stencil-based Path Planners on FPGAs." Proceedings of the ReConFig 2012, Cancun, Mexico 2012. 1-6.
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