An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels

Schmidt M, Fey D (2010)


Publication Type: Conference contribution

Publication year: 2010

Publisher: IEEE Computer Society

Edited Volumes: Proceedings - 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010

City/Town: IEEE, CS Digital Library

Pages Range: 442-447

Conference Proceedings Title: Proceedings of the 6th International Conference on Reconfigurable Computing and FPGAs

Event location: Cancun, Mexico MX

ISBN: 978-0-7695-4314-7

DOI: 10.1109/ReConFig.2010.18

Abstract

Path Planning is one of the most computationally intensive tasks in robot systems and a challenge in dynamically changing environments. By means of FPGAs it is possible to process time-critical and data-intensive tasks in robot systems efficiently. We have developed a parallel path planning algorithm which is based on Marching Pixels, an organic computing principle. The algorithm is optimized for FPGA-based processing. A parallel implementation approach together with an efficient buffering of the map data allowed us to obtain a processing rate suitable for realtime applications, even for higher resolutions. We achieved a processing rate of 80 maps per second for VGA resolution (640×480) on a midsize Virtex-5 FPGA. © 2010 IEEE.

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How to cite

APA:

Schmidt, M., & Fey, D. (2010). An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels. In Proceedings of the 6th International Conference on Reconfigurable Computing and FPGAs (pp. 442-447). Cancun, Mexico, MX: IEEE, CS Digital Library: IEEE Computer Society.

MLA:

Schmidt, Michael, and Dietmar Fey. "An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels." Proceedings of the Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico IEEE, CS Digital Library: IEEE Computer Society, 2010. 442-447.

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