Modeling of Interconnection Networks in Massively Parallel Processor Architectures

Kupriyanov O, Hannig F, Kissler D, Teich J, Lallet J, Sentieys O, Pillement S (2006)

Publication Type: Other publication type

Publication year: 2006

Edited Volumes: Technical Report 05-2006

Authors with CRIS profile

Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011

Involved external institutions

Université de Rennes 1 / University of Rennes 1 FR France (FR)

How to cite

APA:

Kupriyanov, O., Hannig, F., Kissler, D., Teich, J., Lallet, J., Sentieys, O., & Pillement, S. (2006). Modeling of Interconnection Networks in Massively Parallel Processor Architectures.

MLA:

Kupriyanov, Olexiy, et al. Modeling of Interconnection Networks in Massively Parallel Processor Architectures. 2006.

BibTeX: Download