ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Haubelt C, Koch D, Teich J
Verlag: Institute of Electrical and Electronics Engineers Inc.
Jahr der Veröffentlichung: 2003
Tagungsband: Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003)
Seitenbereich: 343-348
ISBN: 9780769520094


Abstract


Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs is presented.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Haubelt, Christian Prof. Dr.-Ing.
Technische Fakultät
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Haubelt, C., Koch, D., & Teich, J. (2003). ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003) (pp. 343-348). São Paulo, BR: Institute of Electrical and Electronics Engineers Inc..

MLA:
Haubelt, Christian, Dirk Koch, and Jürgen Teich. "ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware." Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003, São Paulo Institute of Electrical and Electronics Engineers Inc., 2003. 343-348.

BibTeX: 

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