High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model

Beitrag in einem Sammelwerk


Details zur Publikation

Autor(en): Schmid M, Hannig F, Tanase AP, Teich J
Titel Sammelwerk: Parallel Computing: Accelerating Computational Science and Engineering (CSE)
Verlag: IOS Press
Verlagsort: Amsterdam, The Netherlands
Jahr der Veröffentlichung: 2014
Titel der Reihe: Advances in Parallel Computing
Band: 25
Seitenbereich: 497-506
ISBN: 978-1-61499-380-3
ISSN: 0927-5452
eISSN: 1879-808X


Abstract


The continuous progress in semiconductor technology allows for more and more complex processor architectures. The downside of these technological advances is that computing has already hit a power wall and clock frequencies can barely be increased. In order to scale computing performance in the future, systems' energy efficiency and the degree of parallelism have to be significantly improved. The design of heterogeneous hardware with different specialized resources seems to be a promising solution. When highest performance (throughput, short latencies) and energy efficiency are important, as a remedy, we consider the generation of dedicated FPGA accelerators to address these stringent requirements. In this work, we present the PARO high-level synthesis framework for the automated generation of massively parallel FPGA accelerators. The framework is tailored for compute-intensive applications from the domains of image, video, and other digital signal processing, as well as algorithms from linear algebra. Unique features of PARO include: (1) The design entry in form of a compact and intuitive domain-specific language that is closely related to a mathematical problem description, (2) support for integer, fixed point, floating point, and custom arithmetic, (3) advanced loop transformations (e.g., partitioning) and scheduling techniques in the polyhedron model, (4)generation of accelerator IP cores (VHDL code) that can be easily integrated into a system design such as an SoC or in a networked scenario. Finally, we showcase the capabilities of our framework for the development of a range image conditioning pipeline for smart cameras for range sensing. © 2014 The authors and IOS Press.



FAU-Autoren / FAU-Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Schmid, Moritz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Tanase, Alexandru-Petru Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Schmid, M., Hannig, F., Tanase, A.-P., & Teich, J. (2014). High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. In Parallel Computing: Accelerating Computational Science and Engineering (CSE) (pp. 497-506). Amsterdam, The Netherlands: IOS Press.

MLA:
Schmid, Moritz, et al. "High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model." Parallel Computing: Accelerating Computational Science and Engineering (CSE) Amsterdam, The Netherlands: IOS Press, 2014. 497-506.

BibTeX: 

Zuletzt aktualisiert 2018-10-08 um 00:39