Third party funded individual grant
Acronym: ACoF
Start date : 01.06.2021
Approximate Computing systematically
exploits the trade-off between accuracy, power/energy consumption,
performance, and cost of many applications of daily life, e.g., computer
vision, machine learning, multimedia, big data analysis and gaming.
Computing results approximately is a viable approach here thanks to
inherent human perceptual limitations, redundancy, or noise in input
data.
In this project, we want to investigate novel
techniques for the design and optimization of approximate logic
circuits for FPGA (field-programmable gate array) targets. These devices
are known to perfectly combine high performance of hardware designs
with the reprogrammability of software and are used in many products of
daily life and even cloud servers. The goal of our research is
Approximate Computing systematically exploits the trade-off between accuracy, power/energy consumption, performance, and cost of many applications of daily life, e.g., computer vision, machine learning, multimedia, big data analysis and gaming. Computing results approximately is a viable approach here thanks to inherent human perceptual limitations, redundancy, or noise in input data.In this project, we want to investigate novel techniques for the design and optimization of approximate logic circuits for FPGA (field-programmable gate array) targets. These devices are known to perfectly combine high performance of hardware designs with the re-programmability of software and are used in many products of daily life and even cloud servers. The goal of our research is a) to investigate novel techniques for function approximation exploiting FPGA artifacts, i.e., DPS blocks and BRAM, b) to study new error metrics and a calculus for error propagation in networks of approximate arithmetic modules, c) to develop novel FPGA-specific optimization techniques for design space exploration and synthesis of approximate multi-output Boolean functions, and d) study how to integrate error modeling and analysis techniques into existing high-level programming languages and subsequent synthesis of approximate Verilog or VHDL designs.