Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains

Echavarria Gutiérrez JA, Wildermann S, Keszöcze O, Khosravi F, Becher A, Teich J (2022)


Publication Language: English

Publication Type: Journal article, Original article

Publication year: 2022

Journal

DOI: 10.1515/itit-2021-0040

Abstract

We present the design and a closed-form error analysis of accuracy-configurable multipliers via segmented carry chains. To address this problem, we model the approximate partial-product accumulations as a sequential process. According to a given splitting point of the carry chains, the technique herein discussed allows varying the quality of the accumulations and, consequently, the overall product. Due to these shorter critical paths, such kinds of approximate multipliers can trade-off accuracy for an increased performance whilst exploiting the inherent area savings of sequential over combinatorial approaches. We implemented multiple architectures targeting FPGAs and ASICs with different bit-widths and accuracy configurations to 1) estimate resources, power consumption, and delay, as well as to 2) evaluate those error metrics that belong to the so-called #P-complete class.

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How to cite

APA:

Echavarria Gutiérrez, J.A., Wildermann, S., Keszöcze, O., Khosravi, F., Becher, A., & Teich, J. (2022). Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. it - Information Technology. https://doi.org/10.1515/itit-2021-0040

MLA:

Echavarria Gutiérrez, Jorge Alfonso, et al. "Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains." it - Information Technology (2022).

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