Worst-case energy-consumption analysis by microarchitecture-aware timing analysis for device-driven cyber-physical systems

Raffeck P, Eichler C, Wägemann P, Schröder-Preikschat W (2019)

Publication Type: Conference contribution

Publication year: 2019

Journal

OASIcs : OpenAccess Series in Informatics Schloss Dagstuhl -- Leibniz-Zentrum fuer Informatik

Publisher: Schloss Dagstuhl- Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing

Book Volume: 72

Conference Proceedings Title: OpenAccess Series in Informatics

Event location: Stuttgart DE

ISBN: 9783959771184

DOI: 10.4230/OASIcs.WCET.2019.4

Abstract

Many energy-constrained cyber-physical systems require both timeliness and the execution of tasks within given energy budgets. That is, besides knowledge on worst-case execution time (WCET), the worst-case energy consumption (WCEC) of operations is essential. Unfortunately, WCET analysis approaches are not directly applicable for deriving WCEC bounds in device-driven cyber-physical systems: For example, a single memory operation can lead to a significant power-consumption increase when thereby switching on a device (e.g., transceiver, actuator) in the embedded system. However, as we demonstrate in this paper, existing approaches from microarchitecture-aware timing analysis (i.e., considering cache and pipeline effects) are beneficial for determining WCEC bounds: We extended our framework on whole-system analysis with microarchitecture-aware timing modeling to precisely account for the execution time that devices are kept (in)active. Our evaluations based on a benchmark generator, which is able to output benchmarks with known baselines (i.e., actual WCET and actual WCEC), and an ARM Cortex-M4 platform validate that the approach significantly reduces analysis pessimism in whole-system WCEC analyses.

Authors with CRIS profile

Phillip Raffeck Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme) Christian Eichler Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme) Peter Wägemann Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme) Wolfgang Schröder-Preikschat Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme)

Related research project(s)

Power-Aware Critical Sections (PAX) Jan. 1, 2015 - Sept. 30, 2022 Aspect-Oriented Real-Time Architectures (Phase 2) (AORTA) Aug. 1, 2017 - Sept. 30, 2020

How to cite

APA:

Raffeck, P., Eichler, C., Wägemann, P., & Schröder-Preikschat, W. (2019). Worst-case energy-consumption analysis by microarchitecture-aware timing analysis for device-driven cyber-physical systems. In Sebastian Altmeyer (Eds.), OpenAccess Series in Informatics. Stuttgart, DE: Schloss Dagstuhl- Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing.

MLA:

Raffeck, Phillip, et al. "Worst-case energy-consumption analysis by microarchitecture-aware timing analysis for device-driven cyber-physical systems." Proceedings of the 19th International Workshop on Worst-Case Execution Time Analysis, WCET 2019, Stuttgart Ed. Sebastian Altmeyer, Schloss Dagstuhl- Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing, 2019.

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