Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autor(en): Laukemann J, Hammer J, Hofmann J, Hager G, Wellein G
Verlag: IEEE
Jahr der Veröffentlichung: 2018
Tagungsband: 2018 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS)
Seitenbereich: 121-131
ISBN: 978-1-7281-0182-8


Abstract

An accurate prediction of scheduling and execution of instruction streams is a necessary prerequisite for predicting the in-core performance behavior of throughput-bound loop kernels on out-of-order processor architectures. Such predictions are an indispensable component of analytical performance models, such as the Roofline and the Execution-Cache-Memory (ECM) model, and allow a deep understanding of the performance-relevant interactions between hardware architecture and loop code. We present the Open Source Architecture Code Analyzer (OSACA), a static analysis tool for predicting the execution time of sequential loops comprising x86 instructions under the assumption of an infinite first-level cache and perfect out-of-order scheduling. We show the process of building a machine model from available documentation and semi-automatic benchmarking, and carry it out for the latest Intel Skylake and AMD Zen micro-architectures. To validate the constructed models, we apply them to several assembly kernels and compare runtime predictions with actual measurements. Finally we give an outlook on how the method may be generalized to new architectures.


FAU-Autoren / FAU-Herausgeber

Hager, Georg Dr.
Regionales Rechenzentrum Erlangen (RRZE)
Hammer, Julian
Regionales Rechenzentrum Erlangen (RRZE)
Hofmann, Johannes
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Wellein, Gerhard Prof. Dr.
Professur für Höchstleistungsrechnen


Zitierweisen

APA:
Laukemann, J., Hammer, J., Hofmann, J., Hager, G., & Wellein, G. (2018). Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures. In 2018 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS) (pp. 121-131). Dallas, TX, US: IEEE.

MLA:
Laukemann, Jan, et al. "Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures." Proceedings of the Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, Dallas, TX IEEE, 2018. 121-131.

BibTeX: 

Zuletzt aktualisiert 2019-11-04 um 13:39