Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture

Conference contribution


Publication Details

Author(s): Hager G, Deserno F, Wellein G
Publisher: Springer-Verlag
Publishing place: New York, LLC
Publication year: 2003
Conference Proceedings Title: High Performance Computing in Science and Engineering, Munich 2002: Transactions of the First Joint HLRB and KONWIHR Status and Result Workshop, October 10-11, Technical University of Munich, Germany.
Pages range: 425-442
ISBN: 3540004742


FAU Authors / FAU Editors

Deserno, Frank
Lehrstuhl für Informatik 10 (Systemsimulation)
Hager, Georg Dr.
Regionales Rechenzentrum Erlangen (RRZE)
Wellein, Gerhard Prof. Dr.
Professur für Höchstleistungsrechnen


How to cite

APA:
Hager, G., Deserno, F., & Wellein, G. (2003). Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture. In High Performance Computing in Science and Engineering, Munich 2002: Transactions of the First Joint HLRB and KONWIHR Status and Result Workshop, October 10-11, Technical University of Munich, Germany. (pp. 425-442). München: New York, LLC: Springer-Verlag.

MLA:
Hager, Georg, Frank Deserno, and Gerhard Wellein. "Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture." Proceedings of the High Performance Computing in Science and Engineering, München New York, LLC: Springer-Verlag, 2003. 425-442.

BibTeX: 

Last updated on 2018-10-08 at 12:10