Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures

Roloff S, Schafhauser D, Hannig F, Teich J (2015)

Publication Status: Published

Publication Type: Conference contribution, Conference Contribution

Publication year: 2015

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 44:1-44:6

Article Number: 7167229

Conference Proceedings Title: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

Event location: San Francisco, CA US

ISBN: 9781450335201

DOI: 10.1145/2744769.2744840

Abstract

We present a parallel execution-driven simulator for the efficient simulation of heterogeneous tile-based multi-core architectures. Here, the architecture is composed of several tiles connected via a network-on-chIP and each tile contains local memory as well as several possibly different types of compute resources. Partitioned Global Address Space (PGAS) is a programming model matching very well the needs for programming of such modern multi-core architectures. In order to provide performance estimations for parallel software and enable architecture design space exploration, fast functional and timing simulation techniques are required. Thus, we present a simulator that meets this requirement by combining a fast direct-execution simulation approach with different parallelization strategies. Here, we propose four novel parallel discrete-event simulation techniques, which map thread-level parallelism within the applications to core-level parallelism on the target architecture and back to thread-level parallelism on the host machine. In order to achieve this, the correct synchronization and activation of the host threads is necessary being the main focus of this paper. Experiments with parallel real-world applications are used to compare the different techniques against each other and demonstrate that 10.4 times faster simulations than a sequential simulation can be achieved on a 12-core Intel Xeon processor.

Authors with CRIS profile

Sascha Roloff Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2010 - Dec. 31, 2022 Simulative Design Space Exploration (C02) (SFB/TRR 89 InvasIC (C02)) DFG SFB/Transregio 89 "Invasive Computing" (TRR 89) July 1, 2014 - June 30, 2018

How to cite

APA:

Roloff, S., Schafhauser, D., Hannig, F., & Teich, J. (2015). Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) (pp. 44:1-44:6). San Francisco, CA, US: Institute of Electrical and Electronics Engineers Inc..

MLA:

Roloff, Sascha, et al. "Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures." Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015, San Francisco, CA Institute of Electrical and Electronics Engineers Inc., 2015. 44:1-44:6.

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