Impact of loop tiling on the controller logic of acceleration engines

Conference contribution
(Conference Contribution)


Publication Details

Author(s): Dutta H, Zhai J, Hannig F, Teich J
Publication year: 2009
Conference Proceedings Title: Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP)
Pages range: 161-168
ISBN: 9780769537320


Abstract


High computational effort in modern signal and image processing applications often demands for special purpose accelerators in a system on chip (SoC). New high level synthesis methodologies enable the automated design of such programmable or non-programmable accelerators. Loop tiling is a widely used transformation in such methodologies for dimensioning of such accelerators in order to match inherent massive parallelism of considered algorithms with available functional units and processor elements. Innately, the applications are data-flow dominant and have almost no control flow, but the application of tiling techniques has the disadvantage of a more complex control and communication flow. In this paper, we present a methodology for the automatic generation of the control engines of such accelerators. The controller orchestrates the data transfer and computation. The effect of tiling on area, latency, and power overhead of the controller is studied in detail. It is shown that the controller has a substantial overhead of up to 50% in for different tiling and throughput parameters. The energy-delay product is also used as a metric for identifying optimal accelerator designs. © 2009 IEEE.



FAU Authors / FAU Editors

Dutta, Hritam
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


How to cite

APA:
Dutta, H., Zhai, J., Hannig, F., & Teich, J. (2009). Impact of loop tiling on the controller logic of acceleration engines. In Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (pp. 161-168). Boston, MA, US.

MLA:
Dutta, Hritam, et al. "Impact of loop tiling on the controller logic of acceleration engines." Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009, Boston, MA 2009. 161-168.

BibTeX: 

Last updated on 2018-26-10 at 14:50