Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders

Beitrag in einer Fachzeitschrift
(Originalarbeit)


Details zur Publikation

Autor(en): Echavarria Gutiérrez JA, Wildermann S, Potwigin E, Teich J
Zeitschrift: IEEE Embedded Systems Letters
Jahr der Veröffentlichung: 2017
Heftnummer: Approximate Computing
ISSN: 1943-0663
eISSN: 1943-0671
Sprache: Englisch


Abstract


In this paper, we present a novel methodology to calculate the Arithmetic Error Rate (AER) for deterministic approximate adder architectures where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities. Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the arithmetic error rate for (a) such deterministic approximate adder architectures making use of visibilities and (b) the general case of arbitrarily (also non-uniformly) distributed input bits.



FAU-Autoren / FAU-Herausgeber

Echavarria Gutiérrez, Jorge Alfonso
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Wildermann, Stefan Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Echavarria Gutiérrez, J.A., Wildermann, S., Potwigin, E., & Teich, J. (2017). Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embedded Systems Letters, Approximate Computing. https://dx.doi.org/10.1109/LES.2017.2760922

MLA:
Echavarria Gutiérrez, Jorge Alfonso, et al. "Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders." IEEE Embedded Systems Letters Approximate Computing (2017).

BibTeX: 

Zuletzt aktualisiert 2018-07-07 um 19:23