Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing

Özkan MA, Reiche O, Hannig F, Teich J (2017)

Publication Type: Conference contribution

Publication year: 2017

Pages Range: 155-163

Conference Proceedings Title: 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Event location: Seattle US

ISBN: 978-1-5090-4825-0

URI: https://www12.cs.fau.de/downloads/oezkan/publications/asap17.pdf

DOI: 10.1109/ASAP.2017.7995273

Abstract

Field Programmable Gate Arrays (FPGAs) excel at the implementation of local operators in terms of throughput per energy since the off-chip communication can be reduced with an application-specific on-chip memory configuration. Furthermore, data-level parallelism can efficiently be exploited through so-called loop coarsening, which processes multiple horizontal pixels simultaneously. Moreover, existing solutions for proper border handling in hardware show considerable resource overheads. 
In this paper, we first propose novel architectures for image border handling and loop coarsening, which can significantly reduce area. Second, we present a systematic analysis of these architectures including the formulation of analytical models for their area usage. Based on these models, we provide an algorithm for suggesting the most efficient hardware architecture for a given specification. Finally, we evaluate several implementations of our proposed architectures obtained through Vivado High-Level Synthesis (HLS). The synthesis results show that the proposed coarsening architecture uses 32% less registers for a 5-by-5 convolution with a 64 coarsening factor compared to previous works, whereas the proposed border handling architectures facilitate a decrease in the Look-up Table (LUT) usage by 36%.

Authors with CRIS profile

Mehmet Akif Özkan Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Oliver Reiche Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

GRK 1773: Heterogeneous Image Systems, Project B3 (GRK 1773) RTG 1773: Heterogeneous Image Systems Oct. 1, 2012 - March 31, 2017

How to cite

APA:

Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing. In 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 155-163). Seattle, US.

MLA:

Özkan, Mehmet Akif, et al. "Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing." Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle 2017. 155-163.

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