Task-accurate performance modeling in SystemC for real-time multi-processor architectures
Streubühr M, Falk J, Teich J, Haubelt C, Dorsch R, Schlipf T (2006)
Publication Status: Published
Publication Type: Conference contribution, Conference Contribution
Publication year: 2006
Book Volume: 1
Pages Range: 480-481
Article Number: 1656928
Conference Proceedings Title: Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society
Event location: Munich
ISBN: 9783981080117
URI: https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=34047100936&origin=inward
Abstract
We propose a novel framework, called Virtual Processing Components (VPC), that permits the modeling and simulation of multiple processors running arbitrary scheduling strategies in SystemC. The granularity is given by task accuracy that guarantees a small simulation overhead.
Authors with CRIS profile
Martin Streubühr
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Joachim Falk
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Jürgen Teich
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Christian Haubelt
Technische Fakultät
Related research project(s)
SystemCoDesigner: System level design space exploration for embedded systems (SystemCoDesigner)
April 1, 2005 - April 1, 2008
SysteMoC: Representing models of computation in SystemC (SysteMoC)
April 1, 2005 - April 1, 2008
Involved external institutions
How to cite
APA:
Streubühr, M., Falk, J., Teich, J., Haubelt, C., Dorsch, R., & Schlipf, T. (2006). Task-accurate performance modeling in SystemC for real-time multi-processor architectures. In Proceedings of Design, Automation and Test in Europe (DATE 2006), IEEE Computer Society (pp. 480-481). Munich, DE.
MLA:
Streubühr, Martin, et al. "Task-accurate performance modeling in SystemC for real-time multi-processor architectures." Proceedings of the Design, Automation and Test in Europe, DATE'06, Munich 2006. 480-481.
BibTeX: Download