A flexible Patch-based lattice Boltzmann parallelization approach for heterogeneous GPU-CPU clusters

Feichtinger C, Köstler H, Hager G, Rüde U, Wellein G, Habich J (2011)


Publication Language: English

Publication Type: Journal article, Original article

Publication year: 2011

Journal

Publisher: Elsevier

Book Volume: 37

Pages Range: 536-549

Journal Issue: 9

URI: http://www.sciencedirect.com/science/article/pii/S0167819111000342

DOI: 10.1016/j.parco.2011.03.005

Abstract

Sustaining a large fraction of single GPU performance in parallel computations is considered to be the major problem of GPU-based clusters. We address this issue in the context of a lattice Boltzmann flow solver that is integrated in the WaLBerla software framework. Our multi-GPU implementation uses a block-structured MPI parallelization and is suitable for load balancing and heterogeneous computations on CPUs and GPUs. The overhead required for multi-GPU simulations is discussed in detail. It is demonstrated that a large fraction of the kernel performance can be sustained for weak scaling on InfiniBand clusters, leading to excellent parallel efficiency. However, in strong scaling scenarios using multiple GPUs is much less efficient than running CPU-only simulations on IBM BG/P and x86-based clusters. Hence, a cost analysis must determine the best course of action for a particular simulation task and hardware configuration. Finally we present weak scaling results of heterogeneous simulations conducted on CPUs and GPUs simultaneously, using clusters equipped with varying node configurations. © 2011 Elsevier B.V. All rights reserved.

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APA:

Feichtinger, C., Köstler, H., Hager, G., Rüde, U., Wellein, G., & Habich, J. (2011). A flexible Patch-based lattice Boltzmann parallelization approach for heterogeneous GPU-CPU clusters. Parallel Computing, 37(9), 536-549. https://dx.doi.org/10.1016/j.parco.2011.03.005

MLA:

Feichtinger, Christian, et al. "A flexible Patch-based lattice Boltzmann parallelization approach for heterogeneous GPU-CPU clusters." Parallel Computing 37.9 (2011): 536-549.

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