Optimization of Dynamic Hardware Reconfigurations
Fekete SP, Schepers J, Teich J (2001)
Publication Type: Journal article
Publication year: 2001
Journal
Publisher: Springer Verlag (Germany)
Pages Range: 57-75
Journal Issue: Vol. 19, No. 1
Abstract
Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.
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Germany (DE)How to cite
APA:
Fekete, S.P., Schepers, J., & Teich, J. (2001). Optimization of Dynamic Hardware Reconfigurations. Journal of Supercomputing, Vol. 19, No. 1, 57-75. https://doi.org/10.1023/A:1011188411132
MLA:
Fekete, Sandor P., Jörg Schepers, and Jürgen Teich. "Optimization of Dynamic Hardware Reconfigurations." Journal of Supercomputing Vol. 19, No. 1 (2001): 57-75.
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