Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment

Wust D, Biglari M, Knödtel J, Reichenbach M, Söll C, Fey D (2017)


Publication Language: English

Publication Type: Conference contribution, Original article

Publication year: 2017

Publisher: IEEE

Pages Range: 1-7

Conference Proceedings Title: Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on

Event location: Thessaloniki GR

ISBN: 978-1-5090-6462-5

URI: http://ieeexplore.ieee.org/document/8106978/

DOI: 10.1109/PATMOS.2017.8106978

Abstract

Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom designs. The testing environment is comprised of two main components: a dedicated hardware interface circuit for steering discrete memristor devices and a memory controller as IP core establishing the communication with the hardware interface utilizing an easy-to-use AXI interface. Furthermore, in order to integrate the prototyping platform in processing systems a C API is supplied. This testing environment lays the foundation for integrating memristors in future hybrid CMOS-based SoCs. The platform is put into practice for evaluating a ternary processor on physical hardware using memristors as multi-level storage cells.

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How to cite

APA:

Wust, D., Biglari, M., Knödtel, J., Reichenbach, M., Söll, C., & Fey, D. (2017). Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on (pp. 1-7). Thessaloniki, GR: IEEE.

MLA:

Wust, Daniel, et al. "Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment." Proceedings of the International Symposium on Power and Timing Modeling, Optimization and Simulation, Thessaloniki IEEE, 2017. 1-7.

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