Efficient event-driven simulation of parallel processor architectures

Beitrag bei einer Tagung
(Konferenzbeitrag)


Details zur Publikation

Autorinnen und Autoren: Kupriyanov O, Kissler D, Hannig F, Teich J
Jahr der Veröffentlichung: 2007
Band: 235
Tagungsband: Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Seitenbereich: 71-80


Abstract


In this paper we present a new approach for generating high-speed optimized event-driven instruction set level simulators for adaptive massively parallel processor architectures. The simulator generator is part of a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The generation of high-speed cycle-accurate simulators is of utmost importance here, because they are directly used both for parallel processor architecture debugging and evaluation purposes, as well as during time-consuming architecture/compiler co-exploration. We developed a modeling environment which automatically generates a C++ simulation model either from a graphical input or directly from an XML-based architecture description. Here, we focus on the underlying event-driven simulation model and present our modeling environment, in particular the features of the graphical parallel processor architecture editor and the automatic instruction set level simulator generator. Finally, in a case-study, we demonstrate the pertinence of our approach by simulating different processor arrays. The superior performance of the generated simulators compared to existing simulators and simulator generation approaches is shown.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Zitierweisen

APA:
Kupriyanov, O., Kissler, D., Hannig, F., & Teich, J. (2007). Efficient event-driven simulation of parallel processor architectures. In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 71-80). Nice, FR.

MLA:
Kupriyanov, Olexiy, et al. "Efficient event-driven simulation of parallel processor architectures." Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2007, Nice 2007. 71-80.

BibTeX: 

Zuletzt aktualisiert 2018-23-11 um 06:07