Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning

Schmidt B, Ziener D, Teich J (2014)

Publication Type: Conference contribution

Publication year: 2014

Publisher: IEEE Computer Society

Edited Volumes: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS

Pages Range: 299-304

Conference Proceedings Title: Proc. of the Reconfigurable Architectures Workshop (RAW)

Event location: Phoenix US

DOI: 10.1109/IPDPSW.2014.41

Abstract

Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also state-restoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits may be reduced by up to 48.5% in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.

Authors with CRIS profile

Bernhard Schmidt Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Daniel Ziener Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Reliable FPGA-based Adaptive Systems for Space and Avionics Applications (SatFPGA) April 1, 2013 - Dec. 31, 2014

How to cite

APA:

Schmidt, B., Ziener, D., & Teich, J. (2014). Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. In Proc. of the Reconfigurable Architectures Workshop (RAW) (pp. 299-304). Phoenix, US: IEEE Computer Society.

MLA:

Schmidt, Bernhard, Daniel Ziener, and Jürgen Teich. "Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning." Proceedings of the Reconfigurable Architectures Workshop (RAW), Phoenix IEEE Computer Society, 2014. 299-304.

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