Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs

Conference contribution


Publication Details

Author(s): Schmid M, Ziener D, Teich J
Title edited volumes: Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
Publisher: IEEE Press
Publishing place: New York
Publication year: 2008
Conference Proceedings Title: Proceedings of IEEE International Conference on Field-Programmable Technology
Pages range: 209-216


Abstract


This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs). In this way, we tightly integrate the watermark with the design so that simply removing mark carrying components would damage the intellectual property core. Converting functional LUTs to LUT-based RAMs or shift registers prevents deletion due to optimization. With this technique, we take watermark carrying components out of the scope of optimization algorithms to achieve complete transparency towards development environments. We can extract the marks from the bitfile of an FPGA. The method was tested on a Xil-inx Virtex-II Pro FPGA and showed low overhead in terms of timing and resources at a reasonable number of watermarked cells. © 2008 IEEE.



FAU Authors / FAU Editors

Schmid, Moritz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Ziener, Daniel Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


How to cite

APA:
Schmid, M., Ziener, D., & Teich, J. (2008). Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs. In Proceedings of IEEE International Conference on Field-Programmable Technology (pp. 209-216). Taipei, TW: New York: IEEE Press.

MLA:
Schmid, Moritz, Daniel Ziener, and Jürgen Teich. "Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs." Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT ), Taipei New York: IEEE Press, 2008. 209-216.

BibTeX: 

Last updated on 2018-19-04 at 02:50