Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures

Wolinski C, Kuchcinski K, Teich J, Hannig F (2008)

Publication Type: Conference contribution

Publication year: 2008

Publisher: IEEE Press

Edited Volumes: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

City/Town: New York

Pages Range: 391-396

Conference Proceedings Title: Proceedings of the International Conference on Field Programmable Logic and Applications

Event location: Heidelberg DE

DOI: 10.1109/FPL.2008.4629969

Abstract

In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average). ©2008 IEEE.

Authors with CRIS profile

Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

Involved external institutions

Université de Rennes 1 / University of Rennes 1 FR France (FR) Lund University / Lunds universitet SE Sweden (SE)

How to cite

APA:

Wolinski, C., Kuchcinski, K., Teich, J., & Hannig, F. (2008). Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures. In Proceedings of the International Conference on Field Programmable Logic and Applications (pp. 391-396). Heidelberg, DE: New York: IEEE Press.

MLA:

Wolinski, Christophe, et al. "Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures." Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Heidelberg New York: IEEE Press, 2008. 391-396.

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