A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing

Dutta H, Hannig F, Heigl B, Hornegger H, Teich J (2006)

Publication Type: Conference contribution

Publication year: 2006

Journal

International Conference on Application-Specific Systems, Architectures and Processors, Proceedings Institute of Electrical and Electronics Engineers

Publisher: Institute of Electrical and Electronics Engineers

Edited Volumes: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Pages Range: 331-337

Conference Proceedings Title: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors

Event location: Steamboat Springs, CO US

ISBN: 978-0-7695-2682-9

DOI: 10.1109/ASAP.2006.4

Abstract

Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design. © 2006 IEEE.

Authors with CRIS profile

Hritam Dutta Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Co-Design of Massively Parallel Embedded Processor Architectures (CoMap) Jan. 1, 2005 - Dec. 31, 2011 Dedizierte massiv parallele Systeme (PARO) Jan. 3, 2000 - Jan. 3, 2003

Involved external institutions

Siemens AG, Healthcare Sector DE Germany (DE)

How to cite

APA:

Dutta, H., Hannig, F., Heigl, B., Hornegger, H., & Teich, J. (2006). A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. In Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (pp. 331-337). Steamboat Springs, CO, US: Institute of Electrical and Electronics Engineers.

MLA:

Dutta, Hritam, et al. "A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing." Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP), Steamboat Springs, CO Institute of Electrical and Electronics Engineers, 2006. 331-337.

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