Techniques for on-demand structural redundancy for massively parallel processor arrays

Journal article
(Original article)

Publication Details

Author(s): Teich J, Lari V, Tanase AP, Witterauf M, Khosravi F, Meyer B
Journal: Journal of Systems Architecture
Publisher: Elsevier
Publication year: 2015
Volume: 61
Journal issue: 10
Pages range: 615-627
ISSN: 1383-7621


In this paper, we present techniques for providing on-demand structural redundancy for Coarse-Grained Reconfigurable Array (CGRAs) and a calculus for determining the gains of reliability when applying these replication techniques from the perspective of safety-critical parallel loop program applications. Here, for protecting massively parallel loop computations against errors like soft errors, well-known replication schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) must be applied to each single Processor Element (PE) rather than one based on application requirements for reliability and Soft Error Rates (SERs). Moreover, different voting options and signal replication schemes are investigated. It will be shown that hardware voting may be accomplished at negligible hardware cost, i. e. less than two percent area overhead per PE, for a class of reconfigurable processor arrays called Tightly Coupled Processor Arrays (TCPAs). As a major contribution of this paper, a formal analysis of the reliability achievable by each combination of replication and voting scheme for parallel loop executions on CGRAs in dependence of a given SER and application timing characteristics (schedule) is elaborated. Using this analysis, error detection latencies may be computed and proper decisions which replication scheme to choose at runtime to guarantee a maximal probability of failure on-demand can be derived. Finally, fault-simulation results are provided and compared with the formal analysis of reliability.

FAU Authors / FAU Editors

Khosravi, Faramarz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lari, Vahid
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Tanase, Alexandru-Petru Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Witterauf, Michael
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

External institutions with authors

McGill University

How to cite

Teich, J., Lari, V., Tanase, A.-P., Witterauf, M., Khosravi, F., & Meyer, B. (2015). Techniques for on-demand structural redundancy for massively parallel processor arrays. Journal of Systems Architecture, 61(10), 615-627.

Teich, Jürgen, et al. "Techniques for on-demand structural redundancy for massively parallel processor arrays." Journal of Systems Architecture 61.10 (2015): 615-627.


Last updated on 2018-08-10 at 21:50