Data access characteristics and optimizations for SUN ULTRASPARC T2 AND T2+ systems

Hager G, Zeiser T, Wellein G (2008)


Publication Language: English

Publication Type: Journal article

Publication year: 2008

Journal

Publisher: World Scientific Publishing Co

Book Volume: 18

Pages Range: 471-490

Journal Issue: 4

DOI: 10.1142/S0129626408003521

Abstract

Processor and system architectures that feature multiple memory controllers and/or ccNUMA characteristics are prone to show bottlenecks and erratic performance numbers on scientific codes. Although cache thrashing, aliasing conflicts, and ccNUMA locality and contention problems are well known for many types of systems, they take on peculiar forms on the new Sun UltraSPARC T2 and T2+ processors, which we use here as prototypical multi-core designs. We analyze performance patterns in low-level and application benchmarks and put some emphasis on a comparison of performance features between T2 and its successor. Furthermore we show ways to circumvent bottlenecks by careful data layout, placement and padding. © 2008 World Scientific Publishing Company.

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How to cite

APA:

Hager, G., Zeiser, T., & Wellein, G. (2008). Data access characteristics and optimizations for SUN ULTRASPARC T2 AND T2+ systems. Parallel Processing Letters, 18(4), 471-490. https://doi.org/10.1142/S0129626408003521

MLA:

Hager, Georg, Thomas Zeiser, and Gerhard Wellein. "Data access characteristics and optimizations for SUN ULTRASPARC T2 AND T2+ systems." Parallel Processing Letters 18.4 (2008): 471-490.

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