Wittmann M, Hager G, Eitzinger J, Wellein G (2010)
Publication Type: Journal article
Publication year: 2010
Publisher: World Scientific Publishing Co
Book Volume: 20
Pages Range: 359-376
Journal Issue: 4
URI: http://arxiv.org/abs/1006.3148
DOI: 10.1142/S0129626410000296
Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling. © 2010 World Scientific Publishing Company.
APA:
Wittmann, M., Hager, G., Eitzinger, J., & Wellein, G. (2010). Leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters. Parallel Processing Letters, 20(4), 359-376. https://dx.doi.org/10.1142/S0129626410000296
MLA:
Wittmann, Markus, et al. "Leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters." Parallel Processing Letters 20.4 (2010): 359-376.
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